; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -arm-parallel-dsp -dce -mtriple=armv7-a -S %s -o - | FileCheck %s

define i64 @sext_acc_1(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @sext_acc_1(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2
; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 2
; CHECK-NEXT:    [[TMP4:%.*]] = sext i32 [[ACC:%.*]] to i64
; CHECK-NEXT:    [[TMP5:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[TMP4]])
; CHECK-NEXT:    ret i64 [[TMP5]]
;
entry:
  %ld.a.0 = load i16, ptr %a
  %sext.a.0 = sext i16 %ld.a.0 to i32
  %ld.b.0 = load i16, ptr %b
  %sext.b.0 = sext i16 %ld.b.0 to i32
  %mul.0 = mul i32 %sext.a.0, %sext.b.0
  %addr.a.1 = getelementptr i16, ptr %a, i32 1
  %addr.b.1 = getelementptr i16, ptr %b, i32 1
  %ld.a.1 = load i16, ptr %addr.a.1
  %sext.a.1 = sext i16 %ld.a.1 to i32
  %ld.b.1 = load i16, ptr %addr.b.1
  %sext.b.1 = sext i16 %ld.b.1 to i32
  %mul.1 = mul i32 %sext.a.1, %sext.b.1
  %sext.mul.0 = sext i32 %mul.0 to i64
  %sext.mul.1 = sext i32 %mul.1 to i64
  %add = add i64 %sext.mul.0, %sext.mul.1
  %sext.acc = sext i32 %acc to i64
  %res = add i64 %add, %sext.acc
  ret i64 %res
}

define i64 @sext_acc_2(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @sext_acc_2(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2
; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 2
; CHECK-NEXT:    [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2
; CHECK-NEXT:    [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ADDR_A_2]], align 2
; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ADDR_B_2]], align 2
; CHECK-NEXT:    [[TMP8:%.*]] = sext i32 [[ACC:%.*]] to i64
; CHECK-NEXT:    [[TMP9:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[TMP8]])
; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP5]], i32 [[TMP7]], i64 [[TMP9]])
; CHECK-NEXT:    ret i64 [[TMP10]]
;
entry:
  %ld.a.0 = load i16, ptr %a
  %sext.a.0 = sext i16 %ld.a.0 to i32
  %ld.b.0 = load i16, ptr %b
  %sext.b.0 = sext i16 %ld.b.0 to i32
  %mul.0 = mul i32 %sext.a.0, %sext.b.0
  %addr.a.1 = getelementptr i16, ptr %a, i32 1
  %addr.b.1 = getelementptr i16, ptr %b, i32 1
  %ld.a.1 = load i16, ptr %addr.a.1
  %sext.a.1 = sext i16 %ld.a.1 to i32
  %ld.b.1 = load i16, ptr %addr.b.1
  %sext.b.1 = sext i16 %ld.b.1 to i32
  %mul.1 = mul i32 %sext.a.1, %sext.b.1
  %sext.mul.0 = sext i32 %mul.0 to i64
  %sext.mul.1 = sext i32 %mul.1 to i64
  %add = add i64 %sext.mul.0, %sext.mul.1
  %sext.acc = sext i32 %acc to i64
  %add.1 = add i64 %add, %sext.acc
  %addr.a.2 = getelementptr i16, ptr %a, i32 2
  %addr.b.2 = getelementptr i16, ptr %b, i32 2
  %ld.a.2 = load i16, ptr %addr.a.2
  %sext.a.2 = sext i16 %ld.a.2 to i32
  %ld.b.2 = load i16, ptr %addr.b.2
  %sext.b.2 = sext i16 %ld.b.2 to i32
  %mul.2 = mul i32 %sext.a.2, %sext.b.2
  %sext.mul.2 = sext i32 %mul.2 to i64
  %addr.a.3 = getelementptr i16, ptr %a, i32 3
  %addr.b.3 = getelementptr i16, ptr %b, i32 3
  %ld.a.3 = load i16, ptr %addr.a.3
  %sext.a.3 = sext i16 %ld.a.3 to i32
  %ld.b.3 = load i16, ptr %addr.b.3
  %sext.b.3 = sext i16 %ld.b.3 to i32
  %mul.3 = mul i32 %sext.a.3, %sext.b.3
  %sext.mul.3 = sext i32 %mul.3 to i64
  %add.2 = add i64 %sext.mul.2, %sext.mul.3
  %add.3 = add i64 %add.1, %add.2
  ret i64 %add.3
}

define i64 @sext_acc_3(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @sext_acc_3(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2
; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 2
; CHECK-NEXT:    [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2
; CHECK-NEXT:    [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ADDR_A_2]], align 2
; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ADDR_B_2]], align 2
; CHECK-NEXT:    [[TMP8:%.*]] = sext i32 [[ACC:%.*]] to i64
; CHECK-NEXT:    [[TMP9:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[TMP8]])
; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP5]], i32 [[TMP7]], i64 [[TMP9]])
; CHECK-NEXT:    ret i64 [[TMP10]]
;
entry:
  %ld.a.0 = load i16, ptr %a
  %sext.a.0 = sext i16 %ld.a.0 to i32
  %ld.b.0 = load i16, ptr %b
  %sext.b.0 = sext i16 %ld.b.0 to i32
  %mul.0 = mul i32 %sext.a.0, %sext.b.0
  %addr.a.1 = getelementptr i16, ptr %a, i32 1
  %addr.b.1 = getelementptr i16, ptr %b, i32 1
  %ld.a.1 = load i16, ptr %addr.a.1
  %sext.a.1 = sext i16 %ld.a.1 to i32
  %ld.b.1 = load i16, ptr %addr.b.1
  %sext.b.1 = sext i16 %ld.b.1 to i32
  %mul.1 = mul i32 %sext.a.1, %sext.b.1
  %sext.mul.0 = sext i32 %mul.0 to i64
  %sext.mul.1 = sext i32 %mul.1 to i64
  %add = add i64 %sext.mul.0, %sext.mul.1
  %addr.a.2 = getelementptr i16, ptr %a, i32 2
  %addr.b.2 = getelementptr i16, ptr %b, i32 2
  %ld.a.2 = load i16, ptr %addr.a.2
  %sext.a.2 = sext i16 %ld.a.2 to i32
  %ld.b.2 = load i16, ptr %addr.b.2
  %sext.b.2 = sext i16 %ld.b.2 to i32
  %mul.2 = mul i32 %sext.a.2, %sext.b.2
  %sext.mul.2 = sext i32 %mul.2 to i64
  %addr.a.3 = getelementptr i16, ptr %a, i32 3
  %addr.b.3 = getelementptr i16, ptr %b, i32 3
  %ld.a.3 = load i16, ptr %addr.a.3
  %sext.a.3 = sext i16 %ld.a.3 to i32
  %ld.b.3 = load i16, ptr %addr.b.3
  %sext.b.3 = sext i16 %ld.b.3 to i32
  %mul.3 = mul i32 %sext.a.3, %sext.b.3
  %sext.mul.3 = sext i32 %mul.3 to i64
  %add.1 = add i64 %sext.mul.2, %sext.mul.3
  %add.2 = add i64 %add, %add.1
  %sext.acc = sext i32 %acc to i64
  %add.3 = add i64 %add.2, %sext.acc
  ret i64 %add.3
}

define i64 @sext_acc_4(ptr %a, ptr %b, i32 %acc) {
; CHECK-LABEL: @sext_acc_4(
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A:%.*]], align 2
; CHECK-NEXT:    [[TMP3:%.*]] = load i32, ptr [[B:%.*]], align 2
; CHECK-NEXT:    [[ADDR_A_2:%.*]] = getelementptr i16, ptr [[A]], i32 2
; CHECK-NEXT:    [[ADDR_B_2:%.*]] = getelementptr i16, ptr [[B]], i32 2
; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[ADDR_A_2]], align 2
; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[ADDR_B_2]], align 2
; CHECK-NEXT:    [[TMP8:%.*]] = sext i32 [[ACC:%.*]] to i64
; CHECK-NEXT:    [[TMP9:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP1]], i32 [[TMP3]], i64 [[TMP8]])
; CHECK-NEXT:    [[TMP10:%.*]] = call i64 @llvm.arm.smlald(i32 [[TMP5]], i32 [[TMP7]], i64 [[TMP9]])
; CHECK-NEXT:    ret i64 [[TMP10]]
;
entry:
  %ld.a.0 = load i16, ptr %a
  %sext.a.0 = sext i16 %ld.a.0 to i32
  %ld.b.0 = load i16, ptr %b
  %sext.b.0 = sext i16 %ld.b.0 to i32
  %mul.0 = mul i32 %sext.a.0, %sext.b.0
  %addr.a.1 = getelementptr i16, ptr %a, i32 1
  %addr.b.1 = getelementptr i16, ptr %b, i32 1
  %ld.a.1 = load i16, ptr %addr.a.1
  %sext.a.1 = sext i16 %ld.a.1 to i32
  %ld.b.1 = load i16, ptr %addr.b.1
  %sext.b.1 = sext i16 %ld.b.1 to i32
  %mul.1 = mul i32 %sext.a.1, %sext.b.1
  %add = add i32 %mul.0, %mul.1
  %sext.add = sext i32 %add to i64
  %addr.a.2 = getelementptr i16, ptr %a, i32 2
  %addr.b.2 = getelementptr i16, ptr %b, i32 2
  %ld.a.2 = load i16, ptr %addr.a.2
  %sext.a.2 = sext i16 %ld.a.2 to i32
  %ld.b.2 = load i16, ptr %addr.b.2
  %sext.b.2 = sext i16 %ld.b.2 to i32
  %mul.2 = mul i32 %sext.a.2, %sext.b.2
  %sext.mul.2 = sext i32 %mul.2 to i64
  %addr.a.3 = getelementptr i16, ptr %a, i32 3
  %addr.b.3 = getelementptr i16, ptr %b, i32 3
  %ld.a.3 = load i16, ptr %addr.a.3
  %sext.a.3 = sext i16 %ld.a.3 to i32
  %ld.b.3 = load i16, ptr %addr.b.3
  %sext.b.3 = sext i16 %ld.b.3 to i32
  %mul.3 = mul i32 %sext.a.3, %sext.b.3
  %sext.mul.3 = sext i32 %mul.3 to i64
  %sext.acc = sext i32 %acc to i64
  %add.1 = add i64 %sext.mul.2, %sext.add
  %add.2 = add i64 %sext.add, %add.1
  %add.3 = add i64 %add.2, %sext.mul.3
  %add.4 = add i64 %add.3, %sext.acc
  ret i64 %add.4
}
